1. Field of the Invention
The present invention relates to a semiconductor device and its defect remedying method and, more particularly, to a technology which is effective if applied to a dynamic RAM (Random Access Memory) having a storage capacity as large as about 16 Mbits.
2. Description of the Prior Art
The development of the dynamic RAM having the large storage capacity of about 16 Mbits is being advanced. An example of the dynamic RAM is described on pp. 67 to 81 of xe2x80x9cNikkei Microdevicexe2x80x9d issued on Mar. 1, 1988 by NIKKEI McGRAW-HILL.
In accordance with the increase in the storage capacity, the memory chip necessarily has its size enlarged. Accordingly, special considerations have to be taken into the drop of the operation speed, which is caused by making the elements finer and by handling the wiring lines. In other words, the realization of the high storage capacity of about 16 Mbits requires development of a new technology which is different from that used for the dynamic RAM of about 1 or 4 Mbits.
An object of the present invention is to provide a semiconductor device which aims at having a large storage capacity.
Another object of the present invention is to provide a semiconductor storage device which realizes the large storage capacity while speeding up the operations.
Still another object of the present invention is to provide a rational defect remedying method for the memory device aiming at the large storage capacity.
The aforementioned and other objects and novel features of the present invention will become apparent from the descriptions to be made in the following with reference to the accompanying drawings.
The representatives of the invention to be disclosed hereinafter will be briefly described in the following.
There is provided a semiconductor memory device having a large storage capacity, in which a semiconductor chip is bisected by its longitudinal center line to form two regions, in which peripheral circuits are arranged in a cross area composed of the longitudinal center portions and the transverse center portions of said two regions, and in which memory arrays are arranged in the four regions which are divided by said cross area. In the cross area, the edges contacting with the memory arrays are arranged with X-decoders and Y-decoders, and the regions of the longitudinal or transverse center portion, which are interposed between the X-decoders, are arranged with a main amplifier, a common source switch circuit, a sense amplifier control signal generator and a mat selection control circuit. Those circuits of the peripheral circuits, which may probably inject minority carriers into a substrate on principle, are arranged on two center lines of the cross area or their vicinities. The memory arrays formed in the four quartered areas of said cross area are constructed of a block of plural memory mats as a unit having the same size as includes the sense amplifiers. The unit memory mat includes a control circuit for generating a variety of timing signals for the memory cell selections on the basis of a mat selection signal. The control circuit is activated by the mat selection signal. The memory mat selection signal is prepared by decoding the address signal inputted through a specific address buffer. Bonding pads are partially or wholly arranged in the regions of said cross area. The bonding pads are bonded to LOC lead frame. Of these bonding pads, a plurality of pads for applying the power voltage of the circuit and the ground potential are arranged at a suitable spacing according to circuit blocks requiring them and are connected to the common LOC lead frame to be fed with the power voltage of the circuit and the ground potential. The four regions quartered by the cross area are arranged with the memory arrays, and the semiconductor chip has its four corners stepped. There is provided an internal drop voltage generator which is made operative in response to the power voltage fed from an external terminal and which includes one or more impedance converting output buffers made receptive of a reference voltage prepared by a reference voltage generator. The internal drop voltage generator is provided for each of the memory array operating voltage and the peripheral circuit operating voltage. The internal drop voltage generator drives an output MOSFET of source-follower type having its gate fed with the signal to be outputted through a level converter for converting the signal to be fed and formed by the internal circuit into a signal level corresponding to the power voltage fed from the external terminal. The drop voltage generated by the internal drop voltage generator is selectively outputted, in the output high impedance state of a data output buffer in a test mode, from the output terminal of the data output buffer through a switch MOSFET to be switched by a signal at the bootstrap voltage or external power voltage level. The selection signal of the word lines or the shared sense amplifiers is prepared by a selector which has its operations controlled by a high voltage prepared by boosting the internal drop voltage. At least one pair of memory cell arrays are arranged symmetrically with respect to the main amplifier, and the main amplifier is selectively connected with the input/output lines of the paired memory cell arrays through a switch circuit to be switched in accordance with the selections of the paired memory cell arrays. The shared sense amplifier is given an operation mode for connecting both the data lines at the selected and unselected sides. The pull-up MOSFET of CMOS structure composed of the sense amplifier, the initial-step circuit of the main amplifier and the input/output lines, the short MOSFET composed of the complementary data lines and the complementary input/output lines, and the MOSFET of diode mode constituting the charge pump circuit are caused to have a low threshold voltage. A pair of parallel bit lines are constructed of the bit line cross type, in which the bit lines are interchanged by using a first metal wiring layer formed over the wiring layer forming the bit lines. The first metal wiring layer also forms the column selection lines, one of which is formed to correspond two pairs of bit lines and folded to overlap from one to other bit line pair at portion different from the cross portion of the bit lines. A step damping region made of a dummy wiring layer is formed between a memory cell array of laminated type and a peripheral circuit.
There is also provided a defect remedying method comprising the steps of: constructing a memory array of a block composed of plurality units of memory mats having the same size and including sense amplifiers; forming redundancy word lines and/or redundancy data lines for each of said memory mats; forming redundancy decoders of a number smaller than the total number of the redundancy word and/or data lines of all of said memory mats and larger than the total number of the redundancy word and/or data lines of each of said memory mats so that said redundancy decoders may be used for each of said memory mats or commonly for said memory mats. Preparatory word lines and/or preparatory column selection lines wired to intersect a plurality of word lines and/or column selection lines, respectively, are formed at the output of a word line or column selector, and the word lines and/or the output lines of the column selector are cut by physical means, when a word line and/or a data line are defective, from the column selection lines corresponding to the defective word line and/or the defective data line and are connected with the preparatory word lines and/or the preparatory column selection lines. When in the multi-bit simultaneous testing mode by the multiplex selection of the column system, only the defective data or column selection line of the data lines or column selection lines is switched to a redundancy data line or a redundancy column selection in a manner to correspond to the memory cell array divided into a plurality of memory blocks. The data lines are divided into a plurality of blocks by one of a specific-bit of the address signals of the row and/or column systems, a block address prepared inside, or the combination of the address signal and the block address, and a defective data line in a defective block only is switched to a redundancy data line by making use of a signal designating the block.
Since the major timing signals are propagated four ways from the center of the chip, according to the means specified above, the lengths of the signal wiring lines, which might otherwise accompany the size-up of the chip, can be substantially shortened to realize the large capacity and the speed-up of the DRAM. The influences to be exerted upon the memory arrays can be minimized by arranging a circuit capable of generating minority carriers on or in the vicinity of the two center lines of the aforementioned cross area. The design and control can be simplified by making a block of the unit memory mats of the same size containing sense amplifiers. The bonding pads are connected with the LOC lead frame so that their arrangement can be optimized. Thanks to the provision of the pads for establishing the circuit power voltage and the ground potential, the power impedance can be dropped. The stress from the resin mold can be dispersed by the steps formed in the corners. Thanks to the provision of the internal drop voltage generator, it is possible to prevent the electrostatic breakdown which might otherwise be caused as a result of the low power consumption and the finer element. Since the voltage is dropped in a manner to correspond to the memory array operating voltage and the peripheral circuit operating voltage, it is possible to increase the power noise margin. The output level is retained and speeded up by driving the output MOSFET with the level change. The internal voltage can be monitored by bringing the data output buffer to the output high-impedance state. The speed-up and the stabilization can be achieved by causing the boost power to form the selection signals for selecting the word lines and the shared sense amplifiers. The circuit can be simplified by causing the main amplifiers to correspond to the plural memory cell arrays. The margin test of the sense amplifiers can be executed by connecting the shared sense amplifiers with the two data lines. The speed-up and the level drop can be minimized by using the MOSFET having a low threshold voltage. The high integration can be attained by interchanging the bit lines using the metal wiring layer formed over the bit lines. The metal wiring layer can also be used as the column selection line. The stepped shock absorbing region can prevent the shortage of the steps in the wiring lines.
As the defect remedying method, the redundancy circuit can be simplified by utilizing the redundancy decoder as the multiple memory mats. The circuit can be simplified and speeded up by switching the defective data line or word line directly to the preparatory data line or word line. The preparatory circuit can be simplified by interchanging only the defective circuit when in the multi-bit simultaneous test most by the multiplex selection of the Y-system. Thus, the defect remedy can be achieved with the simple structure by utilizing the block designating signals.